1. Field of the Invention
The present invention relates to a system used to electrically test integrated circuit devices, and more particularly, to a system used to test integrated circuit devices and a method used by such a system. The devices being tested are referred to devices under test (DUTs).
2. Description of the Related Art
After they have been packaged, and before they are sold, integrated circuit devices, such as Double Data Rate Memories (DDRs) and Synchronous Dynamic Random Access Memories (SDRAMs) are electrically tested. Since the time taken to run the tests is reflected in a product's cost, many attempts have been made to reduce test time.
Generally in order to reduce test time, one piece of equipment simultaneously tests a plurality of DUTs. However, due to structural limitations, only a limited number of channels are provided in the most test equipment. Thus, in general one piece of test equipment can test only a limited number of DUTs.
To overcome this limitation, many attempts have been made to reduce the number of channels required to test DUTs. One way of reducing the number of channels is to connect a plurality of DUTs in parallel to a piece of test equipment and to connect the pins of the DUTs in common. For example, Japanese Patent Laid-open Publication No. 2001-176293 (published on Jun. 29, 2001) discloses a method of testing DUTs using common connections.
Various methods of reducing the number of channels by commonly connected pins have been considered. However, it is very difficult to commonly connect the input/output pins within DUTs. In general the data output signals must be unique, hence, it is generally impossible to commonly connect the input/output pins of the same kinds of DUTs. That is to say, input/output channels are generally connected to input/output pins of DUTs in a one-to-one manner. For example, if a DUT is a ×8 product, eight input/output channels are generally required for one DUT. Accordingly, the number of input/output channels must generally be eight times as many as the number of DUTs which are simultaneously tested.
Since the number of channels required in a test equipment is limited, the number of DUTs which can be simultaneously tested is also limited. Hence, there is a need for a method to simultaneously test more DUTs using a limited number of channels.
Furthermore it is very difficult to adjust the test equipment to the DUTs on case by case basis. Thus, a method of testing a plurality of devices at a same time, which has more test variables is needed.